1. Field of the Invention
The present invention relates to superheterodyne receivers and more particularly to systems for automatic gain control (AGC) used, in the amplifying and tuning (TUNER) stages and in the intermediate frequency (IF) stages of receivers to compensate for the effects of the variation in intensity of the signal picked up.
2. Description of the Prior Art
A conventional system for superheterodyne TV reception can be represented by the block diagram of FIG. 1. The system comprises a wideband amplification stage provided with a first automatic gain control circuit, a tuner circuit for preselecting the signal, a mixer stage for deriving an intermediate frequency signal from the amplified signal provided by said wideband amplification circuit and by said tuner circuit (indicated as a whole in the figure by the (TUNER+HF-AGC) block), a band filter for said intermediate frequency (indicated in the figure by the IF BAND FILTER block) and by an intermediate frequency circuit comprising at least one amplifier provided with a second automatic gain control circuit (indicated in the figure by the IF+IF-AGC STAGE block). The system is such as to maintain constant the amplitude of the output signal V.sub.OUT on variation of the amplitude of the input signal V.sub.IN and for this purpose is provided with a first circuit for automatic control of the gain of the tuner, namely with a HF-AGC, with a second circuit for automatic control of the gain of the intermediate frequency stages, namely with a IF-AGC, and with a dynamic automatic control loop for the overall gain of the input circuit of the receiver using a particular circuit commonly known as TUNER DELAY, as indicated in the diagram of FIG. 1. The voltage V.sub.1 and V.sub.3 regulate respectively the gain of the automatic circuit for control of the gain of the TUNER (HF-AGC), and of the circuit for automatic control of the gain of the intermediate frequency stage (IF-AGC), and these two DC control voltages are respectively stored on two storage capacitors, C.sub.1 and C.sub.2, indicated in the diagram of FIG. 1. The TUNER DELAY circuit constitutes in practice an "open collector" able to absorb a fixed maximum current (e.g. of the order of 2 mA) I.sub.1 in order to discharge the capacitor C.sub.1 (decrease V.sub.1) and reduce the gain of the TUNER which, for low levels of antenna signal, is maximum, with the purpose of improving the noise pattern of the entire reception system. By way of the variable resistor R.sub.T the voltage level V.sub.3 =V.sub.REF (i.e. V.sub.REF depending on R.sub.T) can be chosen, on the attainment of which is activated the TUNER DELAY circuit which absorbs a current I.sub.1 which discharges the capacitor C.sub.1 decreasing the voltage V.sub.1 of the node 1 by an appropriate value V.sub.1 asymptotically towards an asymptotic discharge level determined by the product EQU R.sub.(1-2)eq .multidot.I.sub.1
where ##EQU1## depending on a time constant .tau..sub.1 which is given by: ##EQU2##
This is graphically illustrated in the graph of FIG. 5 while the graphs of FIGS. 2, 3 and 4 show respectively the development of the gain of the TUNER as a function of the voltage V.sub.1, the development of the gain of the IF STAGE as a function of the voltage V.sub.3, and the development of the discharge current I.sub.1 of the capacitor C.sub.1 as a function of the voltage V.sub.3 for various parameters V.sub.REF which can be selected by way of the variation of the parameter R.sub.T.
Assuming that the voltage at the storage node 3 of the circuit for automatic control of the gain of the IF block is equal to a value V.sub.3, i.e. to the insertion limit of the TUNER DELAY block, if the antenna signal undergoes a large sudden increase, for example larger than 10 dB, the gain of the TUNER would not be able to undergo a corresponding instantaneous diminution as the time constant which regulates the operation of the automatic gain control loop is relatively high being, as already seen, given by: ##EQU3## where R.sub.1 and R.sub.2 are the two resistors which form a voltage divider for charging the capacitor C.sub.1 to a predefined voltage for supplying the pilot transistor of the HF-AGC.
Conversely the intermediate frequency stage will respond to this situation of sudden increment in the level of the signal at its input, i.e. at node 5 of FIG. 1, so as nevertheless to maintain constant the output level V.sub.OUT and this will occasion loading of an IF-AGC output storage capacitor C.sub.2 (raising the voltage V.sub.3) and simultaneously reducing the gain of the stage so as to compensate for the increase in level of the signal at its input. The response time of the IF-AGC is greatly less than the response time of the HF-AGC, but the presence of a signal with too high a level at the input node 5 of the IF STAGE creates inter-modulation and cross-modulation problems.
Naturally, when the increase in the level of the antenna signal is relatively slow, the problems do not exist since the HF-AGC is in itself able to contain the increase in the level of the signal at the output node 4 of the TUNER and consequently also at the node 5.
On the other hand, unexpected increases in the level of the antenna signal can occur suddenly and also temporarily, for example through the so-called "fast fading" phenomenon caused by a reflection of the arrival signal for example on the wings of an aircraft in transit.
It is a practical impossibility to reduce the time constant .tau..sub.1 for spurious frequency filtering reasons, which would modulate the output of the TUNER which necessitate the use of a capacitor C.sub.1 of large capacitance.